The present invention relates to techniques for providing increased flexibility to input/output banks with respect to supply voltages, and more particularly, to techniques for allowing an integrated circuit to operate its input and output pins at multiple supply voltages.
In programmable logic devices (PLDs) and field programmable gate arrays (FPGAs), it is common for external terminals of the integrated circuit to be grouped into banks that have independent power supply voltages. For example, a PLD can have 8 banks of external terminals, two banks along each edge of the chip. All of the external terminals in one bank are powered by the same power supply voltage. External terminals of an integrated circuit are often referred to as input/output (I/O) pins.
A PLD uses some of its I/O pins to interface with external configuration and testing devices. The I/O pins used for configuration and testing are mingled with other I/O pins across multiple I/O banks on a single integrated circuit. Because all pins in an I/O bank operate at the same supply voltage, buffers that drive I/O pins used for configuration must operate at the same supply voltage level as buffers that drive other pins in the I/O bank not used for configuration. Because the configuration I/O are spread across multiple I/O banks, all of these I/O banks are locked into operating at the same supply voltage level as the external configuration or testing device.
I/O pins not used for configuration and testing are typically placed in multiple I/O banks so that these I/O pins can operate at different supply voltage levels and different I/O standards. The value of placing I/O pins in multiple banks is greatly reduced if many of the I/O banks are restricted to operating at the supply voltage level of an external configuration or testing device.
Some PLD customers address this problem by using one power supply voltage for a pin in configuration mode and a different power supply voltage for that pin in user mode. However, this technique is not a desirable solution, because it requires the power supply to a pin to dynamically change voltage.
Another technique customers use to address this problem is to have off-chip voltage translators convert configuration voltage values for the supply voltage of an I/O bank. However, this technique is not desirable, because it requires a significant amount of additional board space.
Therefore, it would be desirable to provide techniques for providing increased flexibility to I/O banks with respect to supply voltages without requiring a large amount of board space or limiting the operation of the circuit.